Firmware architecture follows a three-layer design: a hardware abstraction layer (HAL) wrapping TIM peripherals, GPIO, and DMA for step generation; a motion planning layer implementing a look-ahead acceleration planner with trapezoidal velocity profiles and corner rounding; and a command layer that parses buffered G-code blocks into the planner's internal trajectory queue. The planner runs at 1kHz, outputting position setpoints to the step generation ISR running at 40kHz via a double-buffered pipeline.
